A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architecture
Ian N. Dunn, Gerard G.L. MeyerBooks.org participates in affiliate programs including Bookshop.org and the Amazon Services LLC Associates Program. We may earn a commission from qualifying purchases made through links on this page, at no additional cost to you.
Synopsis
Dunn (Mercury Computer Systems) and Meyer (computer engineering, John Hopkins University) present a parallel algorithm synthesis procedure that introduces parameters to control the partitioning and scheduling of computation and communication with the goal of implementing parameterized software components that can be tailored to exploit multiple scalar units within a single processor, hierarchical memories, and different configurations of multiple processors. The second half of the slim volume employs the parallel algorithm synthesis procedure in the design of three new adjustable algorithms for matrix factorization, and compares the results with competing algorithms. Annotation ©2003 Book News, Inc., Portland, OR