Cmos Fractional-N Synthesizers

CMOS Fractional-N Synthesizers starts with a comprehensive introduction to general frequency synthesis. Different architectures and synthesizer building blocks are discussed with their relative importance on synthesizer specifications. The process of synthesizer specification derivation is illustrated with the DCS-1800 standard as a general test case.

The book tackles the design of fractional-N synthesizers in CMOS on circuit level as well as system level. The circuit level focuses on high-speed prescaler design up to 12 GHz in CMOS and on fully integrated, low-phase-noise LC-VCO design. High-Q inductor integration and simulation in CMOS is elaborated and flicker noise minimization techniques are presented, ranging from bias point choice to noise filtering techniques.

On a higher level, a systematic design strategy has been developed that trades off all noise contributions and fast dynamics for integrated capacitance (area). Moreover, a theoretical DeltaSigma phase noise analysis is presented, extended with a fast non-linear analysis method to accurately predict the influence of PLL non-linearities on the spectral purity of the DeltaSigma fractional-N frequency synthesizers.

Examines the design of monolithic CMOS frequency synthesizers that can attain the highest spectral purity and fast switching with moderate power consumption, namely a DS-controlled fractional-N synthesizer. The authors (KU Leuven) first review the requirements of the frequency synthesizer in the DCS-1800 system, then develop high speed frequency dividers, high speed voltage controlled oscillators (VCOs), and a dual-path phase-locked loop (PLL) filter. The final chapter presents a monolithic 1.8 GHz DS fractional-N PLL frequency synthesizer, which may lead to an inexpensive cellular transceiver solution. Annotation (c)2003 Book News, Inc., Portland, OR