Computer Organization and Design: The Hardware/Software Interface

The best-selling computer organization book is thoroughly updated to provide a new focus on the revolutionary change taking place in industry today: the switch from uniprocessor to multicore microprocessors. This new emphasis on parallelism is supported by updates reflecting the newest technologies, with examples highlighting the latest processor designs and benchmarking standards. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies and I/O. Sections on the ARM and x86 architectures are also included.

A companion CD provides a toolkit of simulators and compilers along with tutorials for using them, as well as advanced content for further study and a search utility for finding content on the CD and in the printed text.

• Covers the revolutionary change from sequential to parallel computing, with a new chapter on parallelism and sections in every chapter highlighting parallel hardware and software topics.
• Includes a new appendix by the Chief Scientist and the Director of Architecture of NVIDIA covering the emergence and importance of the modern GPU, describing in detail for the first time the highly parallel, highly multithreaded multiprocessor optimized for visual computing.
• Describes a novel approach to measuring multicore performance--the "Roofline model"--with benchmarks and analysis for the AMD Opteron X4, Intel Xeon 5000, Sun UltraSPARC T2, and IBM Cell.
• Includes new content on Flash memory and Virtual Machines.
• Provides a large, stimulating set of new exercises, covering almost 200 pages.
• Features the AMD Opteron X4 and Intel Nehalem as real-world examples throughout the book.
• Updates all processor performance examples using the SPEC CPU2006 suite.

Patterson-Hennessey's new work offers the most current and comprehensive coverage of the topic and is the only book on the market to include RISC architectures. The book is intended to teach a broader audience the fundamentals of computing including programs, operating systems, and compilers.

The performance of software systems is dramatically affected by how well software designers understand the basic hardware technologies at work in a system. Similarly, hardware designers must understand the far-reaching effects their design decisions have on software applications. For readers in either category, this classic introduction to the field provides a look deep into the computer. It demonstrates the relationships between the software and hardware and focuses on the foundational concepts that are the basis for current computer design.

As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies at work in a computer system. The book presents an entire MIPS instruction set-instruction by instruction-the fundamentals of assembly language, computer arithmetic, pipelining, memory hierarchies, and I/O, and introduces the essentials of network and multiprocessor architectures.

A new aspect of the third edition is the explicit connection between program performance and CPU performance. The authors show how hardware and software components-such as the specific algorithm, programming language, compiler, instruction set architecture, and processor implementation-impact program performance. This edition also digs deeper into related hardware and software issues, offering specific material on the CD for readers with a hardware or software focus. A CD provides a toolkit of simulators and compilers along with tutorials for using them.

Revised Printing Features: Appendix A now in the text; corrections throughout the text; updated links on the CD: Uses standard 32-bit MIPS 32 as the primary teaching ISA: Highlights the latestdevelopments in architecture, Intel IA-32, Power PC 604, Pentium P4, Google's PC cluster, SPEC CPU2000 benchmark suite for processors, vSPEC Web99 benchmark for web, EEMBC benchmark for embedded systems, AMD Opteron memory hierarchy, AMD vs. 1A-64, Intrinsity's FastMATH processor servers: New material for a Hardware Focus, Using logic design conventions, Designing with hardware description languages, Advanced pipelining, Designing with FPGAs, HDL simulators and tutorials, Xilinx CAD tools: New material for a Software Focus, How compilers work, How to optimize compilers, How to implement object oriented languages, History sections on programming languages, compilers, operating systems, and databases: A search engine for both the printed text and CD-only content.

David A. Patterson was the first in his family to graduate from college (1969 A.B UCLA), and he enjoyed it so much that he didn't stop until a PhD, (1976 UCLA). After 4 years developing a wafer-scale computer at Hughes Aircraft, he joined U.C. Berkeley in 1977. He spent 1979 at DEC working on the VAX minicomputer. He and colleagues later developed the Reduced Instruction Set Computer (RISC). By joining forces with IBM’s 801 and Stanford’s MIPS projects, RISC became widespread. In 1984 Sun Microsystems recruited him to start the SPARC architecture. In 1987, Patterson and colleagues wondered if tried building dependable storage systems from the new PC disks. This led to the popular Redundant Array of Inexpensive Disks (RAID). He spent 1989 working on the CM-5 supercomputer. Patterson and colleagues later tried building a supercomputer using standard desktop computers and switches. The resulting Network of Workstations (NOW) project led to cluster technology used by many startups. He is now working on the Recovery Oriented Computing (ROC) project. In the past, he served as Chair of Berkeley's CS Division, Chair and CRA. He is currently serving on the IT advisory committee to the U.S. President and has just been elected President of the ACM. All this resulted in 150 papers, 5 books, and the following honors, some shared with friends: election to the National Academy of Engineering; from the University of California: Outstanding Alumnus Award (UCLA Computer Science Department), McEntyre Award for Excellence in Teaching (Berkeley Computer Science), Distinguished Teaching Award (Berkeley); from ACM: fellow, SIGMOD Test of Time Award, Karlstrom Outstanding Educator Award; from IEEE: fellow, Johnson Information Storage Award, Undergraduate Teaching Award, Mulligan Education Medal, and von Neumann Medal.

John L. Hennessy is the president of Stanford University, where he has been a member of the faculty since 1977 in the departments of electrical engineering and computer science. Hennessy is a fellow of the IEEE and the ACM, a member of the National Academy of Engineering, the National Academy of Science, the American Academy of Arts and Sciences, and the Spanish Royal Academy of Engineering. He received the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and shared the John von Neumann award in 2000 with David Patterson. After completing the project in 1984, he took a one-year leave from the university to co-found MIPS Computer Systems, which developed one of the first commercial RISC microprocessors. After being acquired by Silicon Graphics in 1991, MIPS Technologies became an independent company in 1998, focusing on microprocessors for the embedded marketplace. As of 2004, over 300 million MIPS microprocessors have been shipped in devices ranging from video games and palmtop computers to laser printers and network switches. Hennessy's more recent research at Stanford focuses on the area of designing and exploiting multiprocessors. He helped lead the design of the DASH multiprocessor architecture, the first distributed shared-memory multiprocessors supporting cache coherency, and the basis for several commercial multiprocessor designs, including the Silicon Graphics Origin multiprocessors. Since becoming president of Stanford, revising and updating this text and the more advanced Computer Architecture: A Quantitative Approach has become a primary form of recreation and relaxation.