Dynamic Power Management

Dynamic power management is a design methodology aiming at controlling performance and power levels of digital circuits and systems, with the goal of extending the autonomous operation time of battery-powered systems, providing graceful performance degradation when supply energy is limited, and adapting power dissipation to satisfy environmental constraints.
Dynamic Power Management: Design Techniques and CAD Tools addresses design techniques and computer-aided design solutions for power management. Different approaches are presented and organized in an order related to their applicability to control-units, macro-blocks, digital circuits and electronic systems, respectively. All approaches are based on the principle of exploiting idleness of circuits, systems, or portions thereof. They involve both the detection of idleness conditions and the freezing of power-consuming activities in the idle components.
The book also describes some approaches to system-level power management, including Microsoft's OnNow architecture and the `Advanced Configuration and Power Management' standard proposed by Intel, Microsoft and Toshiba. These approaches migrate power management to the software layer running on hardware platforms, thus providing a flexible and self-configurable solution to adapting the power/performance tradeoff to the needs of mobile (and fixed) computing and communication.
Dynamic Power Management: Design Techniques and CAD Tools is of interest to researchers and developers of computer-aided design tools for integrated circuits and systems, as well as to system designers.

Booknews

Provides a new viewpoint on circuit theory based on the commonly used parameter of digital circuits, the gate delay time, and problems in high-speed CMOS above IGHz clock frequency. Outlines essential guidelines for designing the fastest CMOS circuits, and explains how to design and structure computer-aided designs to deal with above-IGHz circuits. Explains the quantum-mechanical nature of CMOS circuits, helps circuit designers deal with the problems of circuit delay when the gate delay is not a valid concept at high switching speeds, and explains how to design the fastest critical paths. For IC designers and CAD professionals. Annotation c. by Book News, Inc., Portland, Or.