Efficient Branch And Bound Search With Application To Computer-Aided Design

Branch-and-bound search has been known for a long time and has been widely used in solving a variety of problems in computer-aided design (CAD) and many important optimization problems.
In many applications, the classic branch-and-bound search methods perform duplications of computations, or rely on the search decision trees which keep track of the branch-and-bound search processes. In CAD and many other technical fields, the computational cost of constructing branch-and-bound search decision trees in solving large scale problems is prohibitive and duplications of computations are intolerable. Efficient branch-and-bound methods are needed to deal with today's computational challenges. Efficient branch-and-bound methods must not duplicate computations.
Efficient Branch and Bound Search with Application to Computer-Aided Design describes an efficient branch-and-bound method for logic justification, which is fundamental to automatic test pattern generation (ATPG), redundancy identification, logic synthesis, minimization, verification, and other problems in CAD. The method is called justification equivalence, based on the observation that justification processes may share identical subsequent search decision sequences. With justification equivalence, duplication of computations is avoided in the dynamic branch-and-bound search process without using search decision trees.
Efficient Branch and Bound Search with Application to Computer-Aided Design consists of two parts. The first part, containing the first three chapters, provides the theoretical work. The second part deals with applications, particularly ATPG for sequential circuits.
This book is particularly useful to readers who are interested in the design and test of digital circuits.

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Addresses the prohibitive computational cost of either decision- making or duplication when applying branch-and-bound search techniques to CAD problems, by introducing Justification Equivalence, an efficient method for logic justification, which is fundamental to automatic test pattern generation, redundancy identification, logic synthesis, minimization, verification, and other problems in CAD. The method avoids both duplication and decision trees by allowing the justifications processes to share identical subsequent search decision sequences. Includes a sequential circuit automatic test pattern generator on a 3.5" disk for Sun or Hewlett Packard computers. Oriented to people designing electronic circuits. Annotation c. Book News, Inc., Portland, OR (booknews.com)