System-on-a-Chip Verification: Methodology and Techniques

This is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign-off. All the verification aspects in this exciting new book are illustrated with a single reference design for Bluetooth application.

...topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief...

System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:

• Explanation of the objective involved in performing verification after a given design step;
• Features of options available;
• When to use a particular option;
• How to select an option; and
• Limitations of the option.

Booknews

The combination of previously separate elements into one lone chip presents engineers with challenges to traditional verification approaches. This guide provides a series of tools and techniques that can be employed for system-on-chip (SOC) verification and design error reduction. The authors, who work for Cadence Design Systems, walk through system level and block verification, simulation, hardware/software co-verification, static netlist verification, and physical verification technologies. Particular attention is paid to newer techniques<-->such as testbench migration, formal model and equivalence checking, linting, and code coverage<-->and the material is illustrated by examples based on a Bluetooth SOC design. Annotation c. Book News, Inc., Portland, OR (booknews.com)

Prakash Rashinkar Cadence Design Systems, Inc., San Jose, CA, USA.

Peter Paterson Cadence Design Systems, Inc., San Jose, CA, USA.

Leena Singh Cadence Design Systems, Inc., San Jose, CA, USA.