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Verilog Digital System Design: RT Level Synthesis, Testbench and Verification by Zainalabedin Navabi — book cover

Verilog Digital System Design: RT Level Synthesis, Testbench and Verification

by Zainalabedin Navabi
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Overview

This rigorous text shows electronics designers and students how to deploy Verilog in sophisticated digital systems design.The Second Edition is completely updated — along with the many worked examples — for Verilog 2001, new synthesis standards and coverage of the new OVI verification library.

About the Author, Zainalabedin Navabi

Zainalabedin Navabi (Boston, MA) is Professor of Electrical and Computer Engineering at Northeastern University. He is the author of Verilog Digital System Design.

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Book Details

Published
September 28, 2005
Publisher
McGraw-Hill Professional Publishing
Format
Hardcover
ISBN
9780071445658

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