Computer Programming, Electrical & Electronic Engineering, Mathematics, Mathematical Analysis, Electrical & Electronic Engineering, Computers - General & Miscellaneous
A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures
Ian N. Dunn, Gerard G.L. Meyer
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Overview
Dunn (Mercury Computer Systems) and Meyer (computer engineering, John Hopkins University) present a parallel algorithm synthesis procedure that introduces parameters to control the partitioning and scheduling of computation and communication with the goal of implementing parameterized software components that can be tailored to exploit multiple scalar units within a single processor, hierarchical memories, and different configurations of multiple processors. The second half of the slim volume employs the parallel algorithm synthesis procedure in the design of three new adjustable algorithms for matrix factorization, and compares the results with competing algorithms. Annotation ©2003 Book News, Inc., Portland, ORBook Details
Published
December 31, 2012
Publisher
Springer-Verlag New York, LLC
Pages
119
Format
Paperback
ISBN
9781461346586