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Electronics - Circuits - Integrated, Electronics - Circuits - General
Applied Formal Verification: For Digital Circuit Design by Douglas L. Perry β€” book cover

Applied Formal Verification: For Digital Circuit Design

by Douglas L. Perry, Harry Foster
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Overview

Formal Verification, ASAP

Applied Formal Verification delivers right-now methods for integrating this powerful tool into your design process. Written by two of the field's leaders, this tutorial opens shortcuts to the concept-proving, efficiency-boosting benefits of formal verification. The book includes real-world examples of formal verification applied to complex designs and clarifying explanations of high-level requirement writing. If you've some knowledge of Verilog or VHDL and simulation verification, you're ready to build your real-world problem-solving skills with this potent guide to formal verification.

APPLY FORMAL VERIFICATION NOW

Simulation-based verification
β€’ Introduction to formal techniques
β€’ Contrasting simulation and formal techniques
β€’ Developing a formal test plan
β€’ Writing high-level requirements
β€’ Proving high-level requirements
β€’ System-level simulation
β€’ Final system simulation
β€’ PSL tables
β€’ SystemVerilog assertions tables

Synopsis

Intended for hardware design engineers, this book introduces general verification techniques, compares them with formal verification techniques, and provides instructions for creating formal high level requirement. The authors discuss formal verification concepts for both applied Boolean and sequential verification, formal property checking, the process of creating a formal test plan, and state reduction techniques. The appendices list commonly used PSL statements for high level requirements and similar requirements specified in System Verilog syntax. Annotation ©2005 Book News, Inc., Portland, OR

About the Author, Douglas L. Perry

Douglas L. Perry is the Director of Marketing for Virtutech, Inc. He is the author of four editions of McGraw-Hill's VHDL. He lives in San Ramon, California.

Harry D. Foster serves as Chairman of the Accellera Formal Verification Technical Committee, which is currently defining the PSL (Property Specification Language) standard. He is co-author of the new Kluwer Academic Publishers book Assertion-Based Design. The Chief Methodologist at Jasper Design, Mr. Foster formerly was Verplex Systems' Chief Architect. He lives in Richardson, Texas.

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Book Details

Published
April 1, 2005
Publisher
McGraw-Hill Companies, The
Pages
240
Format
Hardcover
ISBN
9780071443722

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