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Logic Synthesis for Low Power VLSI Designs

Name: Logic Synthesis for Low Power VLSI Designs
Author: Sasan Iman
ISBN: 9781461374909

by Sasan Iman, Massoud Pedram

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Overview

Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-independent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints. Logic Synthesis for Low Power VLSI Designs in written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.

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Provides a detailed presentation of methodologies, algorithms, and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Topics include two-level logic minimization in PLAs, technology dependent optimization for low power, and the power optimization and synthesis environment (POSE). Intended for VLSI design engineers, CAD professionals, and students who have a basic knowledge of CMOS digital design and logic synthesis. Annotation c. by Book News, Inc., Portland, Or.