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Verification by Error Modeling: Using Testing Techniques in Hardware Verification by Radecka, Katarzyna , Zilic, Zeljko — book cover
Electronics - Circuits - Integrated, CAD/CAM Related Product Design, Computer Mathematics, Electronics - Circuits - VLSI, CAD/CAM

Verification by Error Modeling: Using Testing Techniques in Hardware Verification

by Radecka, Katarzyna, Zilic, Zeljko
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Overview

This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.

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Book Details

Published
December 7, 2010
Publisher
Springer-Verlag New York, LLC
Pages
233
Format
Paperback
ISBN
9781441954022

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